package GCD

import chisel3._ 

class GCD extends Module{
    val io = IO(new Bundle{
        val a       = Input(UInt(16.W))
        val b       = Input(UInt(16.W))
        val load    = Input(Bool())
        val out     = Output(UInt(16.W))
        val valid   = Output(Bool())
    })
    val x = Reg(UInt())
    val y = Reg(UInt())
    when(io.load){
        x:= io.a; y := io.b
    }.otherwise{
        when(x>y){
            x:= x-y
        }.elsewhen(x<=y){
            y:= y-x
        }
    }

    io.out      := x
    io.valid    := y=== 0.U
}

// import chisel3.stage.ChiselStage
// object u_GCD extends App{
//     (new ChiselStage).emitVerilog(new GCD)
// }

import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import firrtl.options.TargetDirAnnotation
 
object u_GCD extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog"),
    Seq(ChiselGeneratorAnnotation(() => new GCD()),
      TargetDirAnnotation("Verilog"))
  )
}